Emitter-Coupled Logic (ECL)

Emitter-Coupled Logic (ECL)

Emitter-Coupled Logic (ECL): The ECL family is the fastest logic family in the group of bipolar logic families. The characteristic features that give this logic family its high speed or short propagation delay are outlined as follows:

  1. It is a nonsaturating logic. That is, the transistors in this logic are always operated in the active region of their output characteristics. They are never driven to either cut-off or saturation, which means that logic LOW and HIGH states correspond to different states of conduction of various bipolar transistors.
  2. The logic swing, that is, the difference in the voltage levels corresponding to logic LOW and HIGH states, is kept small (typically 0.85 V), with the result that the output capacitance needs to be charged and discharged by a relatively much smaller voltage differential.
  3. The circuit currents are relatively high and the output impedance is low, with the result that the output capacitance can be charged and discharged quickly.

ECL has been around since the early 1960s. The transistor logic has a major drawback of speed constraint that is overcome in emitter-coupled logic (ECL). Emitter-coupled logic is used only when necessary for its high speed. In ECL, the transistors are neither cut-off nor in the active region. When the transistors are in the active region, the charge stored in the base region of the transistors is kept to a minimum. This allows short-duration turn-off. The propagation delay of emitter-coupled logic varies from 1ns to 0.5 ns. The circuit of an emitter-coupled pair is shown in the Figure below.

Emitter-coupled pair, Emitter-Coupled Logic (ECL)
Emitter-coupled pair

The emitters of the two transistors are connected together. The base of second transistor is connected to a reference voltage (VR) and the input voltage is applied to base of transistor Q1. When the input voltage is LOW, then the transistor Q1 is cut-off and Q2 will be conducting and the emitter voltage will be:

VE = VR – VBE = VR – 0.75

The input voltage can be increased to 0.65 yet maintain Q1 in OFF state.

V_{in}max=V_{E}+V_{BE\gamma }=V_{R}-0.75+0.65=V_{R}-0.10 volts

When the input voltage is higher than this value then Q1 is turned ON. This causes an increase in the current thereby raising the voltage at the emitters. This voltage drives Q2 to OFF state. The input voltage rises only a little bit before Q2 turns OFF entirely. The minimum high level input voltage occurs when

V_{E}=V_{R}-0.65 V_{in}min=V_{E}+0.75 =V_{R}+0.10

A complete reversal is caused by a 200 mV swing at the input that makes the transistor ON and OFF.

ECL Subfamilies

There are many subfamilies. They differ in characteristics such as propagation delay, power dissipation per gate, and speed-power product. The ECL subfamilies do not include as wide a  range of general purpose logic gates is do TTL and CMOS families. They do, however, include many complex special purpose circuits used in high speed digital data transmission, arithmetic units, and memories.

The first ECL series marketed by Motorola was the MECL-I series. It was followed by MECL-II series. Both these series are now obsolete. The MECL-III series carrying MC1600 numbers, the MECL10K series carrying MC10000 numbers, and the recent MECL10KH series with MC10H000 numbers are in use presently.

Salient Features of Emitter-Coupled Logic (ECL)

There are many features possessed by MECL family devices other than their high speed characteristics that make them attractive for many high-performance applications. The major ones are as follows:

  1. ECL family devices produce the true and complementary output of the intended function simultaneously at the outputs without the use of any external inverters. This in turn reduces package count, reduces power requirements and also minimizes problems arising out of time delays that would be caused by external inverters.
  2. The ECL gate structure inherently has high input impedance and low output impedance, which is very conducive to achieving large fan-out and drive capability.
  3. ECL devices with open emitter outputs allow them to have transmission line drive capability. The outputs match any line impedance. Also, the absence of any pull-down resistors saves power.
  4. ECL devices produce a near-constant current drain on the power supply, which simplifies power supply design.
  5. On account of the differential amplifier design, ECL devices offer a wide performance flexibility, which allows ECL circuits to be used both as linear and as digital circuits.
  6. Termination of unused inputs is easy. Resistors of approximately 50 kΩ allow unused inputs to remain unconnected.


There are several disadvantages associated with ECL. They use a negative power supply that makes it incompatible with any other logic family causing inconvenience in analysis and measurement. ECL requires large currents and small noise margins. They have stable power supply currents when compared to TTL switches thereby reducing noise on the power leads.

Resistor-Transistor Logic (RTL)

Transistor-Transistor Logic (TTL)

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