CMOS Fabrication

The CMOS (complementary metal-oxide silicon) fabrication technology is recognized as the leader of VLSI systems technology. CMOS provides an inherently low power static circuit technology that has the capability of providing lower power-delay product than bipolar, nMOS, or GaAs technologies.

Types of CMOS fabrication

The four main CMOS fabrication technologies are:

1. p-well process
2. n-well process
3. Twin-tub process
4. Silicon on insulator process

The p-Well CMOS fabrication Process

In this process of CMOS, the structure consists of an n-type substrate in which p-type devices may be formed by suitable masking and diffusion. In order to accommodate n-type devices, a deep p-well is diffused into the n-type substrate as shown in the figure below.

The diffusion must be carried out with special care since the p-well doping concentration and depth with affecting the threshold voltages as well as the breakdown voltages of the n-transistors. To achieve low threshold voltages (0 to 1.0 V), we need either deep well diffusion or high well resistivity. However, deep wells require larger spacing between the n-type and p-type transistors and wires because of lateral diffusion and hence a large chip area.

The p⁺ wells act as substrates for the n-devices within the parent n-substrate and the two areas are electrically isolated.

In summary, typical processing steps are:

1. Defines the areas in which the deep p-well diffusions are to take place.
2. Defines the thin oxide regions, namely those areas where the thick oxide is to be stripped and thin oxide is grown to accommodate p and n-transistors and wires.
3. Used to pattern the polysilicon layer which is deposited after the thin oxide.
4. A p+ mask is now used (to be in effect “Anded” with step 2) to define all areas where p-diffusion is to take place.
5. This is usually performed using the negative form of the p+ mask and defines these areas where n-type diffusion is to take place.
6. Contact cuts are now defined.
7. The metal layer pattern is defined by this mask.
8. An overall passivation (over glass) layer is now applied and this mask is needed to define the openings for access to bonding pads.

The n-Well Process

The n-well fabrication has gained wide acceptance.

N-well CMOS circuits are superior to p-well because of the lower substrate bias effect on transistor threshold voltage and inherently lower parasitic capacitances associated with the source and drain regions. The flow diagram of the fabrication for the nMOS process is illustrated in the figure below.

The n-wells are created in the p-type substrate. The typical processing steps for the fabrication of CMOS devices may be summarized as below:

1. It defines the areas in which the deep n-well diffusions have to take place.
2. It defines the thin oxide regions, i.e., those areas in which the thick oxide layer is to be stripped and thin oxide is to be grown for accommodating n- and p-type transistors and diffusion wires.
3. This mask is used to pattern the polysilicon layer, which is to be deposited after thin oxide.
4. In this, an n+ mask is used to define the areas for all types of diffusion of p-type impurity.
5. It is generally performed using a negative form of n+ mask and with step 2. It is used to define the areas for p-type diffusion.
6. Contact cuts are defined.
7. The metal layer pattern is defined.
8. At this stage, the overall passivation layer is applied and by this mask, openings for bonding pads are defined.

The Twin-Tub Process

A logical extension of the p-well and the n-well approaches is the twin-tub fabrication process.

In this process, we start with a substrate of high resistivity n-type material and then create both n-well and p-well regions.

Through this process, it is possible to preserve the performance of the n-transistors without compromising p-transistors. Doping control is more readily achieved and some relaxation in manufacturing tolerance results. This is particularly important as far as latchup is concerned.

 Twin-Tub Process

The twin-tub process allows two separate tubs to be implanted into very lightly doped silicon. This allows the doping profiles in each tub region to be tailored independently so that neither type of device will suffer from excessive doping effects. The lightly doped silicon is an epitaxially grown layer on a heavily doped silicon substrate. The substrate can be either n-type or p-type. The process sequence for a CMOS twin-tub process is discussed as:

1. The initial wafer is chosen n+ silicon and the initial wafer cleaning and back silicon implantation process takes place.
2. Deposition of near intrinsic V-epitaxial wafer.
3. Grow the nitride sandwich and etch. A reactive ion etching may be done to maintain a sharp edge definition. The nitride is left on the regions to become p-tub.
4. Phosphors in implanted as the n-tub dopant are at low energy and enter the exposed silicon but are masked from the adjacent region by the silicon nitride.
5. The wafers are then selectively oxidized using the LOCOS method over the n-tub regions.
6. The nitride is stripped and boron extras the silicon through the thin oxide but is masked from the n-tub by thicker Si02 layer. Intrinsic self-alignment has taken place in the entire process.
7. Oxide is now stripped and a rapid steam oxide is grown. A separate anneal step is now incorporated. Drive-in the dopants takes place. During this drive-in, lateral diffusion of both n and p dopants takes place. Due to LOCOS, the silicon surface in the two tub regions is not the same and a link at the edge exists.
8. After the tub formation, the formation of field oxide and gates is the same as that for the nMOS process.
9. The threshold adjustment implants can be made into the channel regions of the devices to adjust the threshold voltages of the n and p channel transistors.
10. The sources and drains are self-aligned to the gate. Selective implantation of the n-channel and p-channel source/drains to form n+ regions for the n-channels and implanted into all the sources and drains. This is followed by a selective implant of phosphorus or arsenic into the n-channel source/drain regions sat a higher dose so that it over-compensates the bottom.
11. After the subsequent thermal cycles, the phosphorus or arsenic completely covers the boron vertically and laterally.
12. A phosphorus glass layer (PSG) is taken deposited and windows are etched.
13. Aluminum metallization is defined using dry etching.
14. The final layer is a plasma deposited silicon nitride layer that seals the devices and provides mechanical scratch protection.

The twin-tub CMOS technology provides the basis for separate optimization of the p-type and n-type transistors. The arrangement of an inverter (CMOS) using the twin-tub CMOS Technology is shown in the figure below.

Silicon-on-Insulator (SOI)

A prominent emerging CMOS process is Silicon-On-Insulator (SOI). As the name suggest it is a process where the transistors are fabricated on an insulator. Two main insulators are SiO₂ and sapphire.

Two common types of SOI:

1. Sapphire substrate
2. The silicon-based SOI process

Sapphire substrate

• In sapphire substrate technology, a thin layer of silicon is formed on the sapphire surface. The thin layer of silicon is formed on the sapphire surface. A thin layer of silicon is selectively doped to define different threshold transistors.
• The gate oxide is grown at the top of a thin silicon substrate and then polysilicon gates are defined then nMOS and pMOS transistors are formed by implantation.

Silicon based SOI process

• In the silicon-based SOI process, a silicon substrate is used and buried oxide (BOX) is grown on top of the silicon substrate. A thin silicon layer is then grown on the top of buried oxide and is then selectively implanted to form nMOS and pMOS transistors. The gate, source, and drain regions are defined similarly to the bulk process.
• Sapphire is optically and RF transparent. Hence it can be used in optoelectric areas along with ( group III-V based) light emitters.