RISC and CISC Architecture: Its Characteristics and Advantages

This article about the basic architecture of RISC and CISC. It also contains the basic differences between RISC and CISC in a table format.

Two terms that are likely to be encountered frequently while reading about computer ­architecture are RISC and CISC. RISC stands for Reduced Instruction Set Computer and CISC means Complex Instruction Set Computer. Since a lot of controversy surrounds these two terms, let us try to find out what it is all about.

In the early days of microprocessor development, the trend was to have complex instructions implemented fully using hardware. For example, the multiply instruction is a complex instruction which needs a dedicated hardware multiplier. Because hardware is fast, execution is fast, but with lots of such complex instructions, the hardware budget is naturally high. This is the philosophy and the main feature of CISC.

RISC, on the other hand, views this matter in a different way. On average, the number of complex instructions a computer uses is relatively less. So, why not realize a complex instruction using a set of simple instructions? This is possible, and the advantage is that the hardware budget is much less. The instruction set is also small. However, the software is to be written to realize complex instructions with simple instructions. This amounts to trading software for hardware.

Complicated Instruction Set Computer (CISC) architecture:   

When a Microcontroller has an instruction set that supports many addressing modes for the arithmetic and logical instructions and when there are the memory accesses during the ALU operations and the data transfer instructions, the MCU is said to be possessing CISC-architecture.

CISC provides flexibility in choosing various ways of performing the data transfer, arithmetic, and other operations. For example, it is feasible to add the contents of two registers or add the register and memory or add the bits at two memory addresses in a CISC. Instructions are of the variable number of bytes in the CISC. These can take varying amounts of the time interval for execution. An example is Intel 8096.

Reduced Instruction Set Computer (RISC) microcontroller:   

When a Microcontroller has an instruction set that supports a few addressing modes for the arithmetic and logical instructions and just a few (load, store, push and pop) instructions for the data transfer, the Microcontroller is said to be of RISC architecture. RISC provides no flexibility in choosing the many different ways of performing arithmetic and logic operations. These operations are performed after a load of operands in the registers, and the results of these operations are placed in registers. The register contents are later on stored in the memory.

RISC implements each instruction in a single cycle using a distinct hardwired control. It uses a lesser amount of circuitry. It has less power dissipation. There is a reduced instruction set. Instructions are of a fixed number of bytes and take a fixed amount of time for execution. It has many registers. Therefore, operations can be performed using them. The need for external fetches from the memories is greatly reduced. (An external fetch is to be done by the CPU for an operand more frequently in the CISC). The RISC provides higher performance in computing than the CISC. This is because of little need for external fetches, which takes a significant amount of processor time. High performance is also because of the hardwired implementation of instructions. An example of RISC architecture is the ARM processor family-based MCU.

Difference between RISC & CISC architecture (RISC vs. CISC)

There are two types of CPU architectures: RISC and CISC architecture. A RISC microcontroller such as the PIC18F emphasizes simplicity and efficiency. RISC designs start with a necessary and sufficient instruction set. The purpose of using RISC architecture is to maximize speed by reducing clock cycles per instruction. Almost all computations can be obtained from a few simple operations. The goal of RISC architecture is to maximize the effective speed of a design by performing infrequent operations in software and frequent functions in hardware, thus obtaining a net performance gain. The following list summarizes the typical features of a RISC CPU: The RISC CPU is designed using hardwired control with little or no microcode.

All RISC instructions have fixed formats, so microcode design is not necessary.

• A RISC CPU executes most instructions in a single cycle.
• The instruction set of a RISC CPU typically includes an only register, load, and store instructions. All instructions involving arithmetic operations use registers, and load and store operations are utilized to access memory.
• The instructions have a simple fixed format with few addressing modes.
• A RISC CPU processes several instructions simultaneously and thus includes pipelining.
• The software can take advantage of more concurrency. For example, jumps occur after the execution of the instruction that follows. This allows the RISC CPU to fetch the next instruction during the execution of the current instruction.

RISC CPUs are suitable for embedded applications. Embedded controllers are embedded in the host system. This means that the presence and operation of these controllers are basically hidden from the host system. Typical embedded control applications include office automation systems such as printers.

CISC CPUs such as the Motorola /Freescale HC11 CPU contains a large number of instructions and many addressing modes. In contrast, RISC CPUs such as the PIC18F include a simple instruction set with a few addressing modes. Almost all computations can be obtained from a few simple operations.

In CISC, most instructions can access memory while RISC contains mostly load/store instructions. The complex instruction set of CISC requires a complex control unit, thus requiring microprogrammed implementation. RISC utilizes hardwired control which is faster. CISC is more difficult to pipeline; RISC provides more efficient pipelining.

An advantage of CISC over RISC is that complex programs require fewer instructions in CISC with fewer fetch cycles, while RISC requires a large number of instructions to accomplish the same task with several fetch cycles. However, RISC can significantly improve its performance with a faster clock, more efficient pipelining, and compiler optimization.

Difference between RISC & CISC architecture in table form